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(parent: 83f0124) | patch
microblaze: mm: Flush TLB to ensure correct mapping when higmem ON
authorMichal Simek <michal.simek@xilinx.com>
Wed, 13 Jan 2016 18:37:25 +0000 (19:37 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 22 Jun 2017 13:36:52 +0000 (15:36 +0200)
commita753499d43603d7b882cdd835aea9bc7183457fc
tree10fb2454da121a943580921b24a263464d86b4e3tree | snapshot
parent83f0124ad81e87b74c2f461b1794e57ab5e7fea0commit | diff
microblaze: mm: Flush TLB to ensure correct mapping when higmem ON

MMU contains invalid mapping which wasn't flushed and new mapping
is using the same addresses as previous one. That's why TLB miss is not
happening to get new correct TLB entry and MMU points to incorrect area.

This is replicatable when large files(256MB and more) are copied and
checked.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/microblaze/mm/highmem.c diff | blob | history
Domain: System / Kernel;