am33xx: Correct and clean up ddr_regs struct
authorTom Rini <trini@ti.com>
Mon, 30 Jul 2012 18:49:47 +0000 (11:49 -0700)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:13 +0000 (14:58 +0200)
commita74f0c7cb505d3e2184bfd2ab42c3a6e45a1d54a
tree23885e01becaecb7258d20cb9077c4831877539f
parent82afcc9efd4a734f550381fab311644de2c4c524
am33xx: Correct and clean up ddr_regs struct

The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/include/asm/arch-am33xx/ddr_defs.h