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author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Fri, 2 Dec 2022 21:45:18 +0000 (16:45 -0500)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Fri, 2 Dec 2022 22:12:03 +0000 (17:12 -0500)
commit	a74c5707be279bdddb51fe49aa9383c1ddc99fbe
tree	29eb08fa11bb221c5d728e67fc9c1e38b204fb8c	tree \| snapshot
parent	56b7db9e07f6d792a665a7731f91d5f81be85547	commit \| diff

Fix some test files with executable permissions

35 files changed:

llvm/test/Analysis/CostModel/X86/strided-load-i16.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Analysis/CostModel/X86/strided-load-i32.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Analysis/CostModel/X86/strided-load-i64.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Analysis/CostModel/X86/strided-load-i8.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Analysis/ValueTracking/non-negative-phi-bits.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Bitcode/DISubprogram-v5.ll.bc	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/AArch64/dag-ReplaceAllUsesOfValuesWith.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/AArch64/shrink-wrap.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/X86/evex-to-vex-compress.mir	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/X86/pr47000.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/CodeGen/X86/vecloadextract.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/DebugInfo/COFF/numeric-leaves.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/DebugInfo/X86/debug-info-template-parameter.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/LTO/X86/libcall-overridden-via-alias.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/MC/COFF/lset0.s	[changed mode: 0755->0644]	blob \| history
llvm/test/MC/X86/MMX-32.s	[changed mode: 0755->0644]	blob \| history
llvm/test/MC/X86/X87-32.s	[changed mode: 0755->0644]	blob \| history
llvm/test/MC/X86/X87-64.s	[changed mode: 0755->0644]	blob \| history
llvm/test/Other/Inputs/block-info-only.bc	[changed mode: 0755->0644]	blob \| history
llvm/test/Other/Inputs/no-block-info.bc	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/ConstantHoisting/AArch64/consthoist-unreachable.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/Inline/inlined-loop-metadata.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopRotate/catchret.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopSimplify/do-preheader-dbg.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopSimplify/for-preheader-dbg.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/LoopVectorize/pr38800.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/PGOProfile/Inputs/maxcountzero.proftext	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/PGOProfile/maxcountzero.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/Transforms/RewriteStatepointsForGC/vector-nonlive-clobber.ll	[changed mode: 0755->0644]	blob \| history
llvm/test/tools/llvm-split/scc-const-alias.ll	[changed mode: 0755->0644]	blob \| history

Domain: System / Toolchain;

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