Merge pull request #3629 from Rabenda/riscv-c910
authorZhang Xianyi <traits.zhang@gmail.com>
Thu, 19 May 2022 09:57:19 +0000 (17:57 +0800)
committerGitHub <noreply@github.com>
Thu, 19 May 2022 09:57:19 +0000 (17:57 +0800)
commita720e2ca8a1fc03a09e4fcd839b995031e892e65
tree12d84c3c28be691a7fc8d36219c348c81510ac5e
parented8b377318330c348bb805f623170af14c53e89a
parent8dd4579480c888eb2fd910530568c2760eaf6aaa
Merge pull request #3629 from Rabenda/riscv-c910

riscv: Fix machine recognition for c910v