[X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 24 Mar 2019 16:30:35 +0000 (16:30 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 24 Mar 2019 16:30:35 +0000 (16:30 +0000)
commita71c0ed471eb06e2879d8687b427dcf6333474c3
tree687a03d9a3c4fa413cc8a33d642badac2ad943c3
parent4dc851964c03c37d4c8dc635fc92e34c0ae0eb2f
[X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)

Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets).

Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.

llvm-svn: 356858
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/avx512-vec-cmp.ll
llvm/test/CodeGen/X86/known-bits-vector.ll
llvm/test/CodeGen/X86/psubus.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
llvm/test/CodeGen/X86/vector-reduce-umax.ll
llvm/test/CodeGen/X86/vector-reduce-umin.ll
llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
llvm/test/CodeGen/X86/vector-zext.ll