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(parent: 27974e6) | patch
phy: phy-mtk-tphy: add support mt8195
authorChunfeng Yun <chunfeng.yun@mediatek.com>
Fri, 23 Jul 2021 08:22:42 +0000 (16:22 +0800)
committerVinod Koul <vkoul@kernel.org>
Fri, 6 Aug 2021 11:59:40 +0000 (17:29 +0530)
commita69f29cb50a0069f3442c08fcf21fad55d48f4d2
treeb9b06e53c63299e5363ef54fa957b128f5376714tree | snapshot
parent27974e6208c0c44f89e76fc65ad67f9bc1c279a6commit | diff
phy: phy-mtk-tphy: add support mt8195

The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1627028562-23584-3-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/mediatek/phy-mtk-tphy.c diff | blob | history
Domain: System / Kernel;