drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 21 Apr 2021 15:33:59 +0000 (18:33 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 19 May 2021 08:13:18 +0000 (10:13 +0200)
commita67c80dcb4031c2188fd68e57e1b3b67077b69ce
tree24e3db4c319d938fc7866e826b5fcfef8c9d7340
parent17928443db88bfafbf20b700cf2f65e722d67f6d
drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

commit 04d019961fd15de92874575536310243a0d4c5c5 upstream.

We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
(cherry picked from commit f765a5b48c667bdada5e49d5e0f23f8c0687b21b)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c