[committed] [PR target/109508] Adjust conditional move expansion for SFB
authorJeff Law <jlaw@ventanamicro>
Sun, 16 Apr 2023 15:55:32 +0000 (09:55 -0600)
committerJeff Law <jlaw@ventanamicro>
Sun, 16 Apr 2023 15:56:21 +0000 (09:56 -0600)
commita647198fcf7463a42c8e035a429200e7998735dc
treef0b2a39070f7cf26d4126ed4fac97e7c32734fae
parentf006d1a5a1e136be29c78b96c8742ebd3710f4d0
[committed] [PR target/109508] Adjust conditional move expansion for SFB

Recently the conditional move expander's predicates were loosened for the
benefit of the THEAD processors.  In particular one operand that was
previously "register_operand" is now "reg_or_0_operand".  That's fine for
THEAD, but breaks for SFB which requires a register for that operand.

This results in an ICE when compiling the testcase an SFB target such as
the sifive s76.

This change adjusts the expansion code slightly to copy the value into
a register for SFB.

Bootstrapped and regression tested (c,c++,fortran only) with a toolchain
configured to enable SFB by default.

PR target/109508
gcc/

* config/riscv/riscv.cc (riscv_expand_conditional_move): For
TARGET_SFB_ALU, force the true arm into a register.

gcc/testsuite
* gcc.target/riscv/pr109508.c: New test.
gcc/config/riscv/riscv.cc
gcc/testsuite/gcc.target/riscv/pr109508.c [new file with mode: 0644]