drm/i915/icl: Icelake interrupt register addresses and bits
authorTvrtko Ursulin <tvrtko.ursulin@intel.com>
Tue, 9 Jan 2018 23:23:13 +0000 (21:23 -0200)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 19 Jan 2018 20:05:54 +0000 (18:05 -0200)
commita6358dda29a2caa7967833698e690684a031f10d
treed99f6c7119d438d8aedd769087d87cea96fdbff7
parent5c8ea01830b1e5a29b6a949e6b69eb606d335fa9
drm/i915/icl: Icelake interrupt register addresses and bits

MMIO addresses and register definition for the new interrupt
registers in Gen11.

v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter)
v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio)
v4: Bikeshedding (Paulo).

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180109232336.11029-5-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/i915_reg.h