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(parent: ec5c115) | patch
parisc: disable preemption during local tlb flush
authorSven Schnelle <svens@stackframe.org>
Sat, 9 Oct 2021 18:24:35 +0000 (20:24 +0200)
committerHelge Deller <deller@gmx.de>
Sat, 30 Oct 2021 21:11:00 +0000 (23:11 +0200)
commita5e8ca3783adba89b815fed9fb8e4879e795f656
treeaef97699b7a8c69d71cb9e3d0aab6777ce2f39b1tree | snapshot
parentec5c115050f59114e216212837f1c1ebc54bdfc9commit | diff
parisc: disable preemption during local tlb flush

flush_cache_mm() and flush_cache_range() fetch %sr3 via mfsp().
If it matches mm->context, they flush caches and the TLB. However,
the TLB is cpu-local, so if the code gets preempted shortly after
the mfsp(), and later resumed on another CPU, the wrong TLB is flushed.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
arch/parisc/kernel/cache.c diff | blob | history
Domain: System / Kernel;