cxl/bus: Populate the target list at decoder create
authorDan Williams <dan.j.williams@intel.com>
Thu, 9 Sep 2021 05:13:10 +0000 (22:13 -0700)
committerDan Williams <dan.j.williams@intel.com>
Tue, 21 Sep 2021 21:09:34 +0000 (14:09 -0700)
commita5c25802168993c67a03a6e04142761dfb4a3bf5
tree19a43de1b7ba1aabb1b9ef8bcbe0d2b3bc6816ab
parent67dcdd4d3b832ace448f454c47426f657d648fc5
cxl/bus: Populate the target list at decoder create

As found by cxl_test, the implementation populated the target_list for
the single dport exceptional case, it missed populating the target_list
for the typical multi-dport case. Root decoders always know their target
list at the beginning of time, and even switch-level decoders should
have a target list of one or more zeros by default, depending on the
interleave-ways setting.

Walk the hosting port's dport list and populate based on the passed in
map.

Move devm_cxl_add_passthrough_decoder() out of line now that it does the
work of generating a target_map.

Before:
$ cat /sys/bus/cxl/devices/root2/decoder*/target_list
0

0

After:
$ cat /sys/bus/cxl/devices/root2/decoder*/target_list
0
0,1,2,3
0
0,1,2,3

Where root2 is a CXL topology root object generated by 'cxl_test'.

Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/163116439000.2460985.11713777051267946018.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/acpi.c
drivers/cxl/core/bus.c
drivers/cxl/cxl.h