MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435
authorFlorian Fainelli <f.fainelli@gmail.com>
Thu, 4 Feb 2016 02:14:51 +0000 (18:14 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 9 May 2016 10:00:01 +0000 (12:00 +0200)
commita5b143ec51bbfda3dc385e51f8c404fb415be691
tree6abf1d48b81d7d4d50a53fc159e2c863c43b94df
parentf241265fdcc37a171ba246780462e19960a49e7f
MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435

7435 has 4 7038 L1 base register address for each of its Core + TP (for a total
of 4 threads of execution), add the two missing cells for Core 1. We are
providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they
are, and we can later decide to remap these in software to provide proper
interrupt affinity/parenting.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12378/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/boot/dts/brcm/bcm7435.dtsi