projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2353818) | patch
riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:14 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:36 +0000 (08:24 +0900)
commita5aff9838fc0a6df7f294e2b6b460c0d6a383455
treeb2fa80814539a3377ae9477ffad2060b4392acd6tree | snapshot
parent2353818e72e5771b78feac0fe4ac2a0ce09778b1commit | diff
riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
Domain: System / Kernel;