ACPI: cap off P-state transition latency from buggy BIOSes
authorPallipadi, Venkatesh <venkatesh.pallipadi@intel.com>
Thu, 19 Mar 2009 21:41:40 +0000 (14:41 -0700)
committerLen Brown <len.brown@intel.com>
Sat, 28 Mar 2009 01:21:09 +0000 (21:21 -0400)
commita59d1637eb0e0a37ee0e5c92800c60abe3624e24
tree8cc6a7235fc746bd77da4e756f784d80aff316b0
parent8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84
ACPI: cap off P-state transition latency from buggy BIOSes

Some BIOSes report very high frequency transition latency which are plainly
wrong on CPus that can change frequency using native MSR interface.

One such system is IBM T42 (2327-8ZU) as reported by Owen Taylor and
Rik van Riel.

cpufreq_ondemand driver uses this transition latency to come up with a
reasonable sampling interval to sample CPU usage and with such high
latency value, ondemand sampling interval ends up being very high
(0.5 sec, in this particular case), resulting in performance impact due to
slow response to increasing frequency.

Fix it by capping-off the transition latency to 20uS for native MSR based
frequency transitions.

mjg: We've confirmed that this also helps on the X31

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Acked-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Len Brown <len.brown@intel.com>
arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c