Move the Mips target to storing the ABI in the TargetMachine rather
authorEric Christopher <echristo@gmail.com>
Mon, 26 Jan 2015 17:33:46 +0000 (17:33 +0000)
committerEric Christopher <echristo@gmail.com>
Mon, 26 Jan 2015 17:33:46 +0000 (17:33 +0000)
commita5762816948856ed8a21e2bfd960d5121e8fce4d
treefc333bd6e0501612d3c851efec69466353120a72
parent6e4ed49d792c1f7ab831351d0e44ee2b31b35bdb
Move the Mips target to storing the ABI in the TargetMachine rather
than on MipsSubtargetInfo.

This required a bit of massaging in the MC level to handle this since
MC is a) largely a collection of disparate classes with no hierarchy,
and b) there's no overarching equivalent to the TargetMachine, instead
only the subtarget via MCSubtargetInfo (which is the base class of
TargetSubtargetInfo).

We're now storing the ABI in both the TargetMachine level and in the
MC level because the AsmParser and the TargetStreamer both need to
know what ABI we have to parse assembly and emit objects. The target
streamer has a pointer to the one in the asm parser and is updated
when the asm parser is created. This is fragile as the FIXME comment
notes, but shouldn't be a problem in practice since we always
create an asm parser before attempting to emit object code via the
assembler. The TargetMachine now contains the ABI so that the DataLayout
can be constructed dependent upon ABI.

All testcases have been updated to use the -target-abi command line
flag so that we can set the ABI without using a subtarget feature.

Should be no change visible externally here.

llvm-svn: 227102
55 files changed:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h
llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/Mips/MipsLongBranch.cpp
llvm/lib/Target/Mips/MipsOptionRecord.h
llvm/lib/Target/Mips/MipsSubtarget.cpp
llvm/lib/Target/Mips/MipsSubtarget.h
llvm/lib/Target/Mips/MipsTargetMachine.cpp
llvm/lib/Target/Mips/MipsTargetMachine.h
llvm/lib/Target/Mips/MipsTargetStreamer.h
llvm/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
llvm/test/CodeGen/Mips/abiflags32.ll
llvm/test/CodeGen/Mips/blockaddr.ll
llvm/test/CodeGen/Mips/cconv/arguments-float.ll
llvm/test/CodeGen/Mips/cconv/arguments-fp128.ll
llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
llvm/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll
llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
llvm/test/CodeGen/Mips/cconv/arguments.ll
llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
llvm/test/CodeGen/Mips/cconv/callee-saved.ll
llvm/test/CodeGen/Mips/cconv/memory-layout.ll
llvm/test/CodeGen/Mips/cconv/reserved-space.ll
llvm/test/CodeGen/Mips/cconv/return-float.ll
llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
llvm/test/CodeGen/Mips/cconv/return-struct.ll
llvm/test/CodeGen/Mips/cconv/return.ll
llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
llvm/test/CodeGen/Mips/fpxx.ll
llvm/test/CodeGen/Mips/global-address.ll
llvm/test/CodeGen/Mips/mips64fpldst.ll
llvm/test/CodeGen/Mips/mips64intldst.ll
llvm/test/CodeGen/Mips/named-register-n32.ll
llvm/test/CodeGen/Mips/start-asm-file.ll
llvm/test/MC/Mips/cpload.s
llvm/test/MC/Mips/cpsetup.s
llvm/test/MC/Mips/elf_eflags.s
llvm/test/MC/Mips/elf_reginfo.s
llvm/test/MC/Mips/mips-reginfo-fp64.s
llvm/test/MC/Mips/mips64-register-names-n32-n64.s
llvm/test/MC/Mips/mips64-register-names-o32.s
llvm/test/MC/Mips/nabi-regs.s
llvm/test/MC/Mips/nooddspreg-cmdarg.s
llvm/test/MC/Mips/nooddspreg.s
llvm/test/MC/Mips/oddspreg.s