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[AArch64] Fix encoding for lsl #12 in add/sub immediates
authorDiana Picus <diana.picus@linaro.org>
Mon, 19 Sep 2016 11:10:18 +0000 (11:10 +0000)
committerDiana Picus <diana.picus@linaro.org>
Mon, 19 Sep 2016 11:10:18 +0000 (11:10 +0000)
commita53660e4a3d10aaba01d714a589e8f9b2f20c355
treea5f8f9573310003932d0c7446f47ce870b0e08b3tree | snapshot
parent122d6d74f6f0abf5efd93134ef313b02cb82a792commit | diff
[AArch64] Fix encoding for lsl #12 in add/sub immediates

Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.

Differential Revision: https://reviews.llvm.org/D23930

llvm-svn: 281898
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp diff | blob | history
llvm/test/MC/AArch64/darwin-reloc-addsubimm.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/elf-reloc-addsubimm.s diff | blob | history
llvm/test/MC/AArch64/tls-relocs.s diff | blob | history
Domain: System / Toolchain;