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(parent: a8e5433) | patch
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
authorJernej Skrabec <jernej.skrabec@siol.net>
Thu, 9 Aug 2018 16:52:17 +0000 (18:52 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 27 Aug 2018 07:18:11 +0000 (09:18 +0200)
commita528872dbb87faefda3056023eaaf83f14fdafdf
treea5a2bbaef0280fffd211ce251cf21726d62ea8c8tree | snapshot
parenta8e5433cdc500290b52d26a05056e02c448a413ccommit | diff
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs

It may happen that clock framework finds optimal video PLL rate above
that which is really supported by HW.

User manual doesn't really say what is upper limit for video PLLs on
A83T. Because of that, use the maximum rate defined in BSP clk driver
which is 3 GHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c diff | blob | history
Domain: System / Kernel;