[AArch64] Remove redundant ORRWrs which is generated by zero-extend
authorJingu Kang <jingu.kang@arm.com>
Thu, 30 Sep 2021 14:39:10 +0000 (15:39 +0100)
committerJingu Kang <jingu.kang@arm.com>
Mon, 25 Oct 2021 08:47:07 +0000 (09:47 +0100)
commita502436259307f95e9c95437d8a1d2d07294341c
treed71f54a4658a56b8a8fb6f8e687122a2ea91aba0
parent6fa1b4ff4b05b9b9a432f7310802255c160c8f4f
[AArch64] Remove redundant ORRWrs which is generated by zero-extend

%3:gpr32 = ORRWrs $wzr, %2, 0
%4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32

If AArch64's 32-bit form of instruction defines the source operand of ORRWrs,
we can remove the ORRWrs because the upper 32 bits of the source operand are
set to zero.

Differential Revision: https://reviews.llvm.org/D110841
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll
llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir [new file with mode: 0644]