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SelectionDAG: Teach ComputeKnownBits about VSCALE
authorCraig Topper <craig.topper@sifive.com>
Fri, 26 May 2023 17:48:49 +0000 (10:48 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 26 May 2023 17:48:49 +0000 (10:48 -0700)
commita4f437f012b4be40e9fac5d2e86eae549d3469fe
tree5d3b7f0fc218f508478a30ea31965d13ac695f13tree | snapshot
parent2a84c635f2a1dcb4546a5d751a32eac24103c7e6commit | diff
SelectionDAG: Teach ComputeKnownBits about VSCALE

This reverts commit 9b92f70d4758f75903ce93feaba5098130820d40.  The issue
with the re-applied change was an implicit truncation due to the
multiplication.  Although the operations were converted to `APInt`, the
values were implicitly converted to `long` due to the typing rules.

Fixes: #59594

Differential Revision: https://reviews.llvm.org/D140347
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll diff | blob | history
llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll [new file with mode: 0644] blob
Domain: System / Toolchain;