[PowerPC] Implement the vector extend sign instruction pattern match
authorQingShan Zhang <qshanz@cn.ibm.com>
Fri, 22 Nov 2019 08:55:13 +0000 (08:55 +0000)
committerQingShan Zhang <qshanz@cn.ibm.com>
Fri, 22 Nov 2019 08:58:27 +0000 (08:58 +0000)
commita4cc895aee3b37e196f779883c8398a6cdd7ff68
treecf1e18ec26fc268b249e6fcb366c38376f7e2c60
parent3b901ce36755bf67c62d9ba5866ad9e0ab9f546d
[PowerPC] Implement the vector extend sign instruction pattern match
Power9 has instructions to implement the semantics of SIGN_EXTEND_INREG for vector type.
Mark it as legal and add the match pattern.

Differential Revision: https://reviews.llvm.org/D69601
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/test/CodeGen/PowerPC/vector-extend-sign.ll [new file with mode: 0644]