riscv: abstract out CSR names for supervisor vs machine mode
authorChristoph Hellwig <hch@lst.de>
Mon, 28 Oct 2019 12:10:32 +0000 (13:10 +0100)
committerPaul Walmsley <paul.walmsley@sifive.com>
Tue, 5 Nov 2019 17:20:42 +0000 (09:20 -0800)
commita4c3733d32a72f11dee86d0731d7565aa6ebe22d
tree45a8cdbf56325f37ad1b04c015aa8f9a5c646e9a
parent0c3ac28931d578324e93afab6ee7b740dfdaff6f
riscv: abstract out CSR names for supervisor vs machine mode

Many of the privileged CSRs exist in a supervisor and machine version
that are used very similarly.  Provide versions of the CSR names and
fields that map to either the S-mode or M-mode variant depending on
a new CONFIG_RISCV_M_MODE kconfig symbol.

Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>
and Paul Walmsley <paul.walmsley@sifive.com>.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource, drivers/irqchip
[paul.walmsley@sifive.com: updated to apply]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
21 files changed:
arch/riscv/Kconfig
arch/riscv/include/asm/csr.h
arch/riscv/include/asm/irqflags.h
arch/riscv/include/asm/processor.h
arch/riscv/include/asm/ptrace.h
arch/riscv/include/asm/switch_to.h
arch/riscv/kernel/asm-offsets.c
arch/riscv/kernel/entry.S
arch/riscv/kernel/fpu.S
arch/riscv/kernel/head.S
arch/riscv/kernel/irq.c
arch/riscv/kernel/perf_callchain.c
arch/riscv/kernel/process.c
arch/riscv/kernel/signal.c
arch/riscv/kernel/smp.c
arch/riscv/kernel/traps.c
arch/riscv/lib/uaccess.S
arch/riscv/mm/extable.c
arch/riscv/mm/fault.c
drivers/clocksource/timer-riscv.c
drivers/irqchip/irq-sifive-plic.c