ARM: tegra: remove a conditional for CSITE rate
authorStephen Warren <swarren@nvidia.com>
Fri, 24 Jan 2014 19:46:10 +0000 (12:46 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 3 Feb 2014 16:46:46 +0000 (09:46 -0700)
commita4bcd67c72aabfcc2153f4393cd9108b860d9040
treec7cfa7874568332256fe6e3c5e41c04f9e6f5bf0
parent41447fb2cf2fbeb448b1d606cb13ca1ae84f9737
ARM: tegra: remove a conditional for CSITE rate

There's already an SoC-specific conditional in cpu.h to determine the
PLLP rate. Define the CSITE clock rate inside the same conditional, so
that we can remove a conditional from clock_enable_coresight(). This
means one less place to update the code for new SoCs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/arm720t/tegra-common/cpu.c
arch/arm/cpu/arm720t/tegra-common/cpu.h