Merge branch 'CR_878_SBI_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
authorandy.hu <andy.hu@starfivetech.com>
Thu, 5 May 2022 13:24:02 +0000 (13:24 +0000)
committerandy.hu <andy.hu@starfivetech.com>
Thu, 5 May 2022 13:24:02 +0000 (13:24 +0000)
commita488fdacc792184a2bdfceb1b10c5ee6061f9f13
treeb630f125f25cf53afe69a5c8140f1bbc64e744d8
parentbd539ad8c1958b20906ebd860b941b6a82156ced
parent2e334ea5dc9637799177f672f2dd5c04c1b567e4
Merge branch 'CR_878_SBI_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'

spi: Add clock, reset and pinctrl

See merge request sdk/sft-riscvpi-linux-5.10!41
arch/riscv/boot/dts/starfive/jh7110.dtsi
arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi