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ram: stm32mp1: add support of STM32MP13x
authorPatrick Delaunay <patrick.delaunay@foss.st.com>
Fri, 20 May 2022 16:24:50 +0000 (18:24 +0200)
committerPatrick Delaunay <patrick.delaunay@foss.st.com>
Fri, 17 Jun 2022 08:41:16 +0000 (10:41 +0200)
commita46dce2817f574ee1186cc82a19ca9a99869b349
tree0589833b5c9de92888fe60071500751bb1bfaf99tree | snapshot
parentae3e2c2bf775e935eb08fcc8fee236b1633c6fd0commit | diff
ram: stm32mp1: add support of STM32MP13x

Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt diff | blob | history
drivers/ram/stm32mp1/stm32mp1_ram.c diff | blob | history
Domain: System / Kernel;