Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
authorHans Wennborg <hans@hanshq.net>
Mon, 12 Aug 2019 14:23:13 +0000 (14:23 +0000)
committerHans Wennborg <hans@hanshq.net>
Mon, 12 Aug 2019 14:23:13 +0000 (14:23 +0000)
commita45f301f7a5d0f62910d0ed93c96d221555697c9
tree41fa455129e4bddd79433bca19e28dc6e27b844e
parente011a5b4edf828dcaaa4ab5552b71d2bacaaecab
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"

It caused assertions to fire when building Chromium:

  lib/CodeGen/LiveDebugValues.cpp:331: bool
  {anonymous}::LiveDebugValues::OpenRangesSet::empty() const: Assertion
  `Vars.empty() == VarLocs.empty() && "open ranges are inconsistent"' failed.

See https://crbug.com/992871#c3 for how to reproduce.

> Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.
>
> To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.
>
> Differential Revision: https://reviews.llvm.org/D65673

llvm-svn: 368579
59 files changed:
llvm/lib/CodeGen/MachineBlockPlacement.cpp
llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
llvm/test/CodeGen/AMDGPU/multilevel-break.ll
llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/CodeGen/AMDGPU/wqm.ll
llvm/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
llvm/test/CodeGen/ARM/atomic-cmp.ll
llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
llvm/test/CodeGen/ARM/code-placement.ll
llvm/test/CodeGen/ARM/pr32578.ll
llvm/test/CodeGen/Hexagon/bug6757-endloop.ll
llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
llvm/test/CodeGen/Hexagon/prof-early-if.ll
llvm/test/CodeGen/Hexagon/redundant-branching2.ll
llvm/test/CodeGen/PowerPC/atomics-regression.ll
llvm/test/CodeGen/PowerPC/block-placement-1.mir
llvm/test/CodeGen/PowerPC/cmp_elimination.ll
llvm/test/CodeGen/PowerPC/licm-remat.ll
llvm/test/CodeGen/PowerPC/machine-pre.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/remat.ll
llvm/test/CodeGen/Thumb/consthoist-physical-addr.ll
llvm/test/CodeGen/Thumb/pr42760.ll
llvm/test/CodeGen/X86/block-placement.ll
llvm/test/CodeGen/X86/code_placement.ll
llvm/test/CodeGen/X86/code_placement_ignore_succ_in_inner_loop.ll
llvm/test/CodeGen/X86/code_placement_loop_rotation2.ll
llvm/test/CodeGen/X86/code_placement_no_header_change.ll
llvm/test/CodeGen/X86/conditional-tailcall.ll
llvm/test/CodeGen/X86/loop-blocks.ll
llvm/test/CodeGen/X86/loop-rotate.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
llvm/test/CodeGen/X86/move_latch_to_loop_top.ll
llvm/test/CodeGen/X86/pr38185.ll
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
llvm/test/CodeGen/X86/reverse_branches.ll
llvm/test/CodeGen/X86/speculative-load-hardening.ll
llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
llvm/test/CodeGen/X86/tail-dup-repeat.ll
llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
llvm/test/CodeGen/X86/widen_arith-1.ll
llvm/test/CodeGen/X86/widen_arith-2.ll
llvm/test/CodeGen/X86/widen_arith-3.ll
llvm/test/CodeGen/X86/widen_arith-4.ll
llvm/test/CodeGen/X86/widen_arith-5.ll
llvm/test/CodeGen/X86/widen_arith-6.ll
llvm/test/CodeGen/X86/widen_cast-4.ll
llvm/test/DebugInfo/X86/PR37234.ll
llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll