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(parent: e73b20c) | patch
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 14 Jan 2020 11:20:09 +0000 (11:20 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 14 Jan 2020 11:41:47 +0000 (11:41 +0000)
commita43b0065c5c78eba3fb83881fb628f5b8182db64
tree983d795963a172cda345f34ac75d1b66d6a29190tree | snapshot
parente73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7commit | diff
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.

As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well.

SHL tests / handling will be added in a follow up patch.
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll diff | blob | history
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll diff | blob | history
Domain: System / Toolchain;