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(parent: 89ca3b8) | patch
arm64: Implement cache_line_size() based on CTR_EL0.CWG
authorCatalin Marinas <catalin.marinas@arm.com>
Thu, 3 Apr 2014 16:48:54 +0000 (17:48 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 9 May 2014 14:47:45 +0000 (15:47 +0100)
commita41dc0e841523efe1df7fa5ad48b5e9027a921df
treec162086a45807902dd8c510132f3c3f82603d3e6tree | snapshot
parent89ca3b881987f5a4be4c5dbaa7f0df12bbdde2fdcommit | diff
arm64: Implement cache_line_size() based on CTR_EL0.CWG

The hardware provides the maximum cache line size in the system via the
CTR_EL0.CWG bits. This patch implements the cache_line_size() function
to read such information, together with a sanity check if the statically
defined L1_CACHE_BYTES is smaller than the hardware value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
arch/arm64/Kconfig diff | blob | history
arch/arm64/include/asm/cache.h diff | blob | history
arch/arm64/include/asm/cachetype.h diff | blob | history
arch/arm64/kernel/setup.c diff | blob | history
Domain: System / Kernel;