clk: rockchip: fix wrong mmc sample phase shift for rk3328
authorZiyuan Xu <xzy.xu@rock-chips.com>
Thu, 11 Oct 2018 07:26:43 +0000 (15:26 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Nov 2018 08:19:16 +0000 (09:19 +0100)
commita3eeeed10702c11d4332c5c3366770b5566ff02b
treeef978fc620ad0f1fd6cd3541f3e9be50a77628ea
parent1a2502d376ac047bd4f70a51658993b22513ddfc
clk: rockchip: fix wrong mmc sample phase shift for rk3328

commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648 upstream.

mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/rockchip/clk-rk3328.c