perf/x86/intel/pebs: Add PEBSv3 decoding
authorPeter Zijlstra <peterz@infradead.org>
Tue, 12 May 2015 13:18:18 +0000 (15:18 +0200)
committerIngo Molnar <mingo@kernel.org>
Sun, 7 Jun 2015 14:09:16 +0000 (16:09 +0200)
commita3d86542de8850be52e8589da22b24002941dfb7
tree32f252229099a23651f036ad780cd24cdb58bbe0
parentc4937a91ea56b546234b0608a413ebad90536d26
perf/x86/intel/pebs: Add PEBSv3 decoding

PEBSv3 as present on Skylake fixed the long standing issue of the
status bits. They now really reflect the events that generated the
record.

Tested-by: Andi Kleen <ak@linux.intel.com>
Tested-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel_ds.c