author | Hsiangkai Wang <kai.wang@sifive.com> | |
Fri, 8 Jan 2021 06:42:59 +0000 (14:42 +0800) | ||
committer | Hsiangkai Wang <kai.wang@sifive.com> | |
Wed, 17 Feb 2021 06:05:19 +0000 (14:05 +0800) | ||
commit | a3c783dbf27f0a65472906dafc455b5165ed881a | |
tree | 838a439bd6b84c7be3cefa4634e4b873034c5f07 | tree | snapshot |
parent | 5a31a67385c900244dede8defedacfa4fe79f370 | commit | diff |
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | diff | blob | history | |
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | diff | blob | history | |
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll | [new file with mode: 0644] | blob |