drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculation
authorGeorge Shen <george.shen@amd.com>
Fri, 20 May 2022 15:55:10 +0000 (11:55 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 21 Jun 2022 22:17:24 +0000 (18:17 -0400)
commita3a885878e74d3d81e4742f8dd84faa27c8863ad
tree8d81d97eff03aea7dca2792929bd4d0c0449aead
parent04e6931a76e592e66e1014ffe4d13303ccac5d8b
drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculation

[Why]
Certain use cases will pass in zero in the new_clocks parameter for all
clocks. This results in a divide-by-zero error when attempting to round
up the new clock.

When new_clocks are zero, no rounding is required, so we can skip it.

[How]
Guard the division calculation with a check to make sure clocks are not
zero.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c