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[RISCV] Remove redundant test cases for index segment load (1/8).
authorHsiangkai Wang <kai.wang@sifive.com>
Fri, 19 Feb 2021 03:07:25 +0000 (11:07 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Fri, 19 Feb 2021 03:56:08 +0000 (11:56 +0800)
commita32c79ce2c355decbf6fd06b492044828c1c957d
tree593e9e7818368d13b3b4c687deb3cd4bf5f439e1tree | snapshot
parent3bf8f162a0a922026d4c183231acb2be0dcdfcc7commit | diff
[RISCV] Remove redundant test cases for index segment load (1/8).

Differential Revision: https://reviews.llvm.org/D97020
llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll diff | blob | history
Domain: System / Toolchain;