drivers/perf: arm_pmu: Request PMU SPIs with IRQF_PER_CPU
authorWill Deacon <will.deacon@arm.com>
Tue, 25 Jul 2017 15:30:34 +0000 (16:30 +0100)
committerWill Deacon <will.deacon@arm.com>
Thu, 27 Jul 2017 12:43:22 +0000 (13:43 +0100)
commita3287c41ff405025bc57b165a0f6cd698bbbc1be
tree070b5f8986d50c1a2e72160871937f43f8c359f4
parentd0153c7ff9226535a51e6a81f61656c9500957f4
drivers/perf: arm_pmu: Request PMU SPIs with IRQF_PER_CPU

Since the PMU register interface is banked per CPU, CPU PMU interrrupts
cannot be handled by a CPU other than the one with the PMU asserting the
interrupt. This means that migrating PMU SPIs, as we do during a CPU
hotplug operation doesn't make any sense and can lead to the IRQ being
disabled entirely if we route a spurious IRQ to the new affinity target.

This has been observed in practice on AMD Seattle, where CPUs on the
non-boot cluster appear to take a spurious PMU IRQ when coming online,
which is routed to CPU0 where it cannot be handled.

This patch passes IRQF_PERCPU for PMU SPIs and forcefully sets their
affinity prior to requesting them, ensuring that they cannot
be migrated during hotplug events. This interacts badly with the DB8500
erratum workaround that ping-pongs the interrupt affinity from the handler,
so we avoid passing IRQF_PERCPU in that case by allowing the IRQ flags
to be overridden in the platdata.

Fixes: 3cf7ee98b848 ("drivers/perf: arm_pmu: move irq request/free into probe")
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm/mach-ux500/cpu-db8500.c
drivers/perf/arm_pmu.c
include/linux/perf/arm_pmu.h