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(parent: 94b88c1) | patch
[RISCV] Fix encoding for Zcb instruction c.sh.
authorCraig Topper <craig.topper@sifive.com>
Tue, 27 Jun 2023 16:38:43 +0000 (09:38 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 27 Jun 2023 16:44:50 +0000 (09:44 -0700)
commita32499fba9591075bcf64068fd38dabee8ce921e
treef47ac80cbd4dba34bdf8086f52c2588739c05d6ctree | snapshot
parent94b88c1b9d11ea5dbaf2ca39d9a7ffe778ed65fccommit | diff
[RISCV] Fix encoding for Zcb instruction c.sh.

Bit 6 should be 0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D153793
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td diff | blob | history
llvm/test/MC/RISCV/rv32zcb-valid.s diff | blob | history
Domain: System / Toolchain;