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author	Daniel Sanders <daniel.sanders@imgtec.com>
	Sat, 27 Jun 2015 15:39:19 +0000 (15:39 +0000)
committer	Daniel Sanders <daniel.sanders@imgtec.com>
	Sat, 27 Jun 2015 15:39:19 +0000 (15:39 +0000)
commit	a3134fae172e32e39adde797070868f5faf745eb
tree	865830ad0b7497d965287875ab3d73b855f8934a	tree \| snapshot
parent	8c7e29d583eb54b2dd3e4c105e63ce3b4299433b	commit \| diff

[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.

Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883

44 files changed:

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp		diff \| blob \| history
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp		diff \| blob \| history
llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp		diff \| blob \| history
llvm/lib/Target/Mips/Mips64InstrInfo.td		diff \| blob \| history
llvm/lib/Target/Mips/MipsInstrInfo.td		diff \| blob \| history
llvm/lib/Target/Mips/MipsOptionRecord.h		diff \| blob \| history
llvm/lib/Target/Mips/MipsRegisterInfo.td		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32_le.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r2.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r2_le.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r6.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt		diff \| blob \| history
llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt		diff \| blob \| history
llvm/test/MC/Mips/mips-cop0-reginfo.s	[new file with mode: 0644]	blob
llvm/test/MC/Mips/mips32/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips32r2/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips32r3/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips32r5/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips32r6/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips64/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips64r2/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips64r3/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips64r5/valid.s		diff \| blob \| history
llvm/test/MC/Mips/mips64r6/valid.s		diff \| blob \| history

Domain: System / Toolchain;

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