[VE] Support atomic exchange instructions
authorKazushi (Jam) Marukawa <marukawa@nec.com>
Sat, 12 Dec 2020 03:27:32 +0000 (12:27 +0900)
committerKazushi (Jam) Marukawa <marukawa@nec.com>
Tue, 15 Dec 2020 08:43:11 +0000 (17:43 +0900)
commita2eb07aa55405f6e9bca0a0a31681053147e6540
tree08735f23e6b8d37c75ce0b2ba8b955d405285d08
parent14a91d676b794db09c14abecf363650a8fc90c61
[VE] Support atomic exchange instructions

Support atomic exchange and atomic compare and exchange instructions.
Change CAS and TS1AM instructions for ISel patterns.  Add selectADDRzi
pattern for them.  Add TS1AM pseudo instruction also for better ISel.
Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw
instructions except atomicrmw xchg.  Add custom lower for i8/i16
atomicrmw xchg.  Modify replaceFI to support CAS/TS1AM instructions
which use "reg+disp" operands instead of "reg+imm+disp" operands.
And, add several regression tests to check the correctness.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D93161
llvm/lib/Target/VE/VEISelDAGToDAG.cpp
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
llvm/lib/Target/VE/VEInstrInfo.td
llvm/lib/Target/VE/VERegisterInfo.cpp
llvm/test/CodeGen/VE/Scalar/atomic.ll [new file with mode: 0644]
llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll [new file with mode: 0644]
llvm/test/CodeGen/VE/Scalar/atomic_load.ll
llvm/test/CodeGen/VE/Scalar/atomic_store.ll
llvm/test/CodeGen/VE/Scalar/atomic_swap.ll [new file with mode: 0644]