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(parent: 43cb127) | patch
imx: mx6ul select SYS_L2CACHE_OFF
authorPeng Fan <Peng.Fan@freescale.com>
Mon, 20 Jul 2015 11:28:28 +0000 (19:28 +0800)
committerStefano Babic <sbabic@denx.de>
Sun, 2 Aug 2015 09:05:08 +0000 (11:05 +0200)
commita2c74aaf51171fbdfab725c4dd05b58b1ce45070
tree4a42ddb2bb0954063819ee3f895e6cf05d10b45ftree | snapshot
parent43cb127b75d7511705e14d4d8b761f61d102bde7commit | diff
imx: mx6ul select SYS_L2CACHE_OFF

i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
arch/arm/cpu/armv7/mx6/Kconfig diff | blob | history
Domain: System / Kernel;