drm/amd/display: fix pixel rate update sequence
authorDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Thu, 1 Jun 2023 20:09:32 +0000 (16:09 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 15 Jun 2023 14:45:27 +0000 (10:45 -0400)
commita2c7356f526dba1aa5f49ba17c822e46dcf7d6f6
treeeac436496045595c633cc142d9b2cd5f6ea712b7
parentf4bc8a43069c6268a49f064fdbf85ead5cc2bf04
drm/amd/display: fix pixel rate update sequence

The k1/k2 pixel rate dividers in dccg should only be updated on stream enable
and do not actually depend on whether odm combine is active.

This removes an on flip update of these and fixes the calculate function
to ignore odm status for dp steams.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h