drm/i915: Fix ICL MG PHY vswing handling
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 7 Dec 2020 20:35:11 +0000 (22:35 +0200)
committerJani Nikula <jani.nikula@intel.com>
Tue, 26 Jan 2021 13:45:54 +0000 (15:45 +0200)
commita2a5f5628e5494ca9353f761f7fe783dfa82fb9a
treef96d4e86854b7b0ff37199281e88b33b8f5289b5
parentef99a60ffd9b918354e038bc5e61f007ff7e901d
drm/i915: Fix ICL MG PHY vswing handling

The MH PHY vswing table does have all the entries these days. Get
rid of the old hacks in the code which claim otherwise.

This hack was totally bogus anyway. The correct way to handle the
lack of those two entries would have been to declare our max
vswing and pre-emph to both be level 2.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Fixes: 9f7ffa297978 ("drm/i915/tc/icl: Update TC vswing tables")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201207203512.1718-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 5ec346476e795089b7dac8ab9dcee30c8d80ad84)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_ddi.c