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(parent: eb7e5cf) | patch
drm/amd/display: Fix bug use wrong pp interface
authorRex Zhu <Rex.Zhu@amd.com>
Thu, 16 Aug 2018 03:36:38 +0000 (11:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 24 Aug 2018 16:16:58 +0000 (11:16 -0500)
commita296b16270ab8d3b1c2a41ca1dd4d2fc34b598d9
treed89323df0a1da51ef685191390d385119989559btree | snapshot
parenteb7e5cfced102e61814f6f3e4cb4acb9f9315760commit | diff
drm/amd/display: Fix bug use wrong pp interface

Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.

Pointed out by Francis David <david.francis@amd.com>

v2: dal only need to set min_dcefclk and min_fclk to smu.
    so use display_clock_voltage_request interface,
    instand of update all display configuration.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c diff | blob | history
Domain: System / Kernel;