[RISCV] Add RV32 test cases for vsuxseg.
authorHsiangkai Wang <kai.wang@sifive.com>
Thu, 21 Jan 2021 15:40:50 +0000 (23:40 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 23 Jan 2021 00:54:56 +0000 (08:54 +0800)
commita28755003782b97062b19867cfab201816d8dd5f
tree6942eda9214fa8f8ba73048fc2dc07c511c0c29c
parent66a49aef690cb2980152d3cfa867e797bbda54be
[RISCV] Add RV32 test cases for vsuxseg.

Differential Revision: https://reviews.llvm.org/D95196
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll [new file with mode: 0644]