sparc64: T5 PMU
authorbob picco <bpicco@meloft.net>
Tue, 16 Sep 2014 14:09:06 +0000 (10:09 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 30 Oct 2014 16:38:27 +0000 (09:38 -0700)
commita2613388d68c4bbd8512dc3e3bbdf693106b06aa
tree70cd0e2d529dcce6192148e9cfed6901cd59b51e
parentaf02e9dd14cc732849ca5739d304944a96731a52
sparc64: T5 PMU

The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.

We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.

Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/sparc/include/asm/hypervisor.h
arch/sparc/kernel/hvapi.c
arch/sparc/kernel/hvcalls.S
arch/sparc/kernel/pcr.c
arch/sparc/kernel/perf_event.c