[RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

This miscompile was introduced in D119527.

This was a special pattern for rotate+bswap on RV32. It doesn't
work for RV64 since the rotate needs to be half the bitwidth. The
equivalent pattern for RV64 is ROTR ((GREV x, 56), 32) so match
that instead.

This could be generalized further as noted in the new FIXME.

Reviewed By: Chenbing.Zheng

Differential Revision: https://reviews.llvm.org/D120686