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(parent: 2011052) | patch
llvm-reduce: Add reduction pass to remove regalloc hints
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 20 Apr 2022 15:37:53 +0000 (11:37 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 1 Jun 2022 13:15:41 +0000 (09:15 -0400)
commita0dcbe45bd8387da51f94e4d171c3ecc3d266e64
tree85370b39f3ffaa80150446372a7a86f9c14d8451tree | snapshot
parent2011052150e1a2fb8586b030126f8bec338f4cc5commit | diff
llvm-reduce: Add reduction pass to remove regalloc hints

I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.
llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir diff | blob | history
llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir [new file with mode: 0644] blob
llvm/tools/llvm-reduce/CMakeLists.txt diff | blob | history
llvm/tools/llvm-reduce/DeltaManager.cpp diff | blob | history
llvm/tools/llvm-reduce/ReducerWorkItem.cpp diff | blob | history
llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp [new file with mode: 0644] blob
llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h [new file with mode: 0644] blob
Domain: System / Toolchain;