EDAC/mce_amd: Decode MCA_STATUS in bit definition order
authorYazen Ghannam <yazen.ghannam@amd.com>
Tue, 12 Feb 2019 21:24:29 +0000 (21:24 +0000)
committerBorislav Petkov <bp@suse.de>
Fri, 15 Feb 2019 13:36:31 +0000 (14:36 +0100)
commita0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67
tree380789256dfb507b419ed0bddbcc38e791715219
parent3f4da372ec8e4ce58c17ac4f2e3c8891bbfea17e
EDAC/mce_amd: Decode MCA_STATUS in bit definition order

Sort the MCA_STATUS bits in decode output to follow how they are defined
in the register.

The order is as follows:

  Bit | Decode
  ------------
  62  | Over
  61  | UC
  59  | MiscV
  58  | AddrV
  57  | PCC
  55  | TCC
  53  | SyndV
  46  | CECC
  45  | UECC
  44  | Deferred
  43  | Poison
  40  | Scrub

 [ bp: Massage a bit. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86@kernel.org
Link: https://lkml.kernel.org/r/20190212212417.107049-2-Yazen.Ghannam@amd.com
drivers/edac/mce_amd.c