powerpc/8xxx: Refactor SRIO initialization into common code
authorKumar Gala <galak@kernel.crashing.org>
Thu, 30 Dec 2010 18:09:53 +0000 (12:09 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 14 Jan 2011 07:32:21 +0000 (01:32 -0600)
commita09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b
tree07f0d677a4d7ac227abc90cdbbd90d306641f76e
parent213ac73e2caff8b477c31f85d8132f8cc116f366
powerpc/8xxx: Refactor SRIO initialization into common code

Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO.  We mimic what we do with PCIe
controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
README
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc8xxx/Makefile
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/srio.c [new file with mode: 0644]
arch/powerpc/include/asm/fsl_law.h
board/freescale/corenet_ds/corenet_ds.c
include/configs/corenet_ds.h