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(parent: 3aed95a) | patch
[ARM] Add patterns for VSUB with q and r registers
authorOliver Cruickshank <oliver.cruickshank@arm.com>
Fri, 6 Sep 2019 17:02:42 +0000 (17:02 +0000)
committerOliver Cruickshank <oliver.cruickshank@arm.com>
Fri, 6 Sep 2019 17:02:42 +0000 (17:02 +0000)
commita050307c0572213efa40ffe8a55cfd4b15387543
treeaaf338d0ba03053e45c02d6fab52e4152519dc33tree | snapshot
parent3aed95af4ecdaa9fd76cc9c617c55f4bfbc068b9commit | diff
[ARM] Add patterns for VSUB with q and r registers

Added patterns for VSUB to support q and r registers, which reduces
pressure on q registers.

llvm-svn: 371231
llvm/lib/Target/ARM/ARMInstrMVE.td diff | blob | history
llvm/test/CodeGen/Thumb2/mve-vsubqr.ll [new file with mode: 0644] blob
Domain: System / Toolchain;