x86/perf: Default set FREEZE_ON_SMI for all
authorPeter Zijlstra <peterz@infradead.org>
Thu, 27 Jan 2022 11:32:51 +0000 (12:32 +0100)
committerPeter Zijlstra <peterz@infradead.org>
Wed, 2 Feb 2022 12:11:39 +0000 (13:11 +0100)
commita01994f5e5c79d3a35e5e8cf4252c7f2147323c3
treead6495f3deb0de9b1e807a9fd08275fde256d696
parent26291c54e111ff6ba87a164d85d4a4e134b7315c
x86/perf: Default set FREEZE_ON_SMI for all

Kyle reported that rr[0] has started to malfunction on Comet Lake and
later CPUs due to EFI starting to make use of CPL3 [1] and the PMU
event filtering not distinguishing between regular CPL3 and SMM CPL3.

Since this is a privilege violation, default disable SMM visibility
where possible.

Administrators wanting to observe SMM cycles can easily change this
using the sysfs attribute while regular users don't have access to
this file.

[0] https://rr-project.org/

[1] See the Intel white paper "Trustworthy SMM on the Intel vPro Platform"
at https://bugzilla.kernel.org/attachment.cgi?id=300300, particularly the
end of page 5.

Reported-by: Kyle Huey <me@kylehuey.com>
Suggested-by: Andrew Cooper <Andrew.Cooper3@citrix.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@kernel.org
Link: https://lkml.kernel.org/r/YfKChjX61OW4CkYm@hirez.programming.kicks-ass.net
arch/x86/events/intel/core.c