author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Wed, 8 Jan 2020 01:22:06 +0000 (20:22 -0500) | ||
committer | Matt Arsenault <arsenm2@gmail.com> | |
Thu, 9 Jan 2020 15:29:32 +0000 (10:29 -0500) | ||
commit | 9ffd0ed838191247e0da7df5e28e54a5129e76a7 | |
tree | d5cd6686d07f75b943136774750d3eefe0b5c643 | tree | snapshot |
parent | c66b2e1c87ecde72eb37d3452ec9c1b8766ede30 | commit | diff |
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | diff | blob | history | |
llvm/lib/Target/AMDGPU/SIInstructions.td | diff | blob | history | |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir | [new file with mode: 0644] | blob |
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir | [new file with mode: 0644] | blob |