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[RISCV] Add test cases for i8/i16 abs followed by zext.
authorCraig Topper <craig.topper@sifive.com>
Wed, 21 Dec 2022 20:08:07 +0000 (12:08 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 21 Dec 2022 20:26:01 +0000 (12:26 -0800)
commit9fdf21f3d07d5efafec4334b1b4d200bc7811c05
tree1114250ce1c72643e5c9c1d96ffe1c6d176427d8tree | snapshot
parentdbc92f598ed0ea92a8f0eb4000d3120cc85ad3f5commit | diff
[RISCV] Add test cases for i8/i16 abs followed by zext.

The andi, zext.h and slli+srli shift pairs at the end of the generated
output are unnecessary if the input is sign extended.
llvm/test/CodeGen/RISCV/iabs.ll diff | blob | history
Domain: System / Toolchain;